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DATA SHEET
TDA8358J Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier
Product specification Supersedes data of 1999 Dec 22 2002 Sep 25
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier
FEATURES * Few external components required * High efficiency fully DC-coupled vertical bridge output circuit * Vertical flyback switch with short rise and fall times * Built-in guard circuit * Thermal protection circuit * Improved EMC performance due to differential inputs * East-west output stage. GENERAL DESCRIPTION
TDA8358J
The TDA8358J is a power circuit for use in 90 and 110 colour deflection systems for 25 to 200 Hz field frequencies, and for 4 : 3 and 16 : 9 picture tubes. The IC contains a vertical deflection output circuit, operating as a high efficiency class G system. The full bridge output circuit allows DC coupling of the deflection coil in combination with single positive supply voltages. The east-west output stage is able to supply the sink current for a diode modulator circuit. The IC is constructed in a Low Voltage DMOS (LVDMOS) process that combines bipolar, CMOS and DMOS devices. DMOS transistors are used in the output stage because of absence of second breakdown.
QUICK REFERENCE DATA SYMBOL Supplies VP VFB Iq(P)(av) Iq(FB)(av) Ptot Vi(p-p) Io(p-p) Flyback switch Io(peak) Vo VI(bias) Io Tstg Tamb Tj maximum (peak) output current t 1.5 ms - - 2 - -55 -25 - - - - - - - - 1.8 68 3.2 750 A supply voltage flyback supply voltage average quiescent supply current average quiescent flyback supply current total power dissipation during scan during scan 7.5 2 x VP - - - - - 12 45 10 - - 1000 - 18 66 15 10 15 V V mA mA W PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Inputs and outputs input voltage (peak-to-peak value) output current (peak-to-peak value) 1500 3.2 mV A
East-west amplifier output voltage input bias voltage output current V V mA C C C
Thermal data; in accordance with IEC 747-1 storage temperature ambient temperature junction temperature +150 +85 +150
2002 Sep 25
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Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier
ORDERING INFORMATION TYPE NUMBER TDA8358J BLOCK DIAGRAM PACKAGE NAME DBS13P DESCRIPTION
TDA8358J
VERSION SOT141-6
plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm)
handbook, full pagewidth
COMP 13 COMP. CIRCUIT
GUARD 11 GUARD CIRCUIT
VP 3
VFB 9
M5 D2 D3 M2 Vi(p-p) D1 VI(bias) 0 INPUT AND FEEDBACK CIRCUIT INB 2 M1 4 M3 Ii(p-p) II(av) 0 6 VGND 7 EWGND
MGL866
INA 1 M4
10 OUTA
12
FEEDB
Vi(p-p) VI(bias) 0
OUTB
TDA8358J
INEW 5
M6
8 OUTEW
Fig.1 Block diagram.
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3
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier
PINNING SYMBOL INA INB VP OUTB INEW VGND EWGND OUTEW VFB OUTA GUARD FEEDB COMP PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 DESCRIPTION positive vertical input negative vertical input supply voltage vertical output voltage B east-west input voltage vertical ground east-west ground east-west output voltage flyback supply voltage vertical output voltage A guard output voltage input measuring resistor input compensation current FUNCTIONAL DESCRIPTION Vertical output stage
TDA8358J
The vertical driver circuit has a bridge configuration. The deflection coil is connected between the complimentary driven output amplifiers. The differential input circuit is voltage driven. The input circuit is specially designed for direct connection to driver circuits delivering a differential signal but it is also suitable for single-ended applications. For processors with output currents, the currents are converted to voltages by the conversion resistors RCV1 and RCV2 (see Fig.3) connected to pins INA and INB. The differential input voltage is compared with the voltage across the measuring resistor RM, thus providing feedback information. The voltage across RM is proportional with the output current. The relationship between the differential input voltage and the output current is defined by: Vi(dif)(p-p) = Io(p-p) x RM; Vi(dif)(p-p) = VINA - VINB The output current should not exceed 3.2 A (p-p) and is determined by the value of RM and RCV. The allowable input voltage range is 100 mV to 1.6 V for each input. The formula given does not include internal bondwire resistances. Depending on the value of RM and the internal bondwire resistance (typical value 50 m) the actual value of the current in the deflection coil will be about 5% lower than calculated. Flyback supply
handbook, halfpage
INA INB VP OUTB INEW VGND EWGND OUTEW VFB
1 2 3 4 5 6
TDA8358J
7 8 9
OUTA 10 GUARD 11 FEEDB 12 COMP 13
MGL867
The flyback voltage is determined by the flyback supply voltage VFB. The principle of two supply voltages (class G) allows to use an optimum supply voltage VP for scan and an optimum flyback supply voltage VFB for flyback, thus very high efficiency is achieved. The available flyback output voltage across the coil is almost equal to VFB, due to the absence of a coupling capacitor which is not required in a bridge configuration. The very short rise and fall times of the flyback switch are determined mainly by the slew rate value of more than 300 V/s. Protection The output circuit contains protection circuits for: * Too high die temperature * Overvoltage of output A.
The die has been glued to the metal block of the package. If the metal block is not insulated from the heatsink, the heatsink shall only be connected directly to pin VGND.
Fig.2 Pin configuration.
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Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier
Guard circuit A guard circuit with output pin GUARD is provided. The guard circuit generates a HIGH-level during the flyback period. The guard circuit is also activated for one of the following conditions: * During thermal protection (Tj 170 C) * During an open-loop condition. The guard signal can be used for blanking the picture tube and signalling fault conditions. The vertical synchronization pulses of the guard signal can be used by an On Screen Display (OSD) microcontroller. Damping resistor compensation HF loop stability is achieved by connecting a damping resistor RD1 (see Fig.4) across the deflection coil. The current values in RD1 during scan and flyback are significantly different. Both the resistor current and the deflection coil current flow into measuring resistor RM, resulting in a too low deflection coil current at the start of the scan. The difference in the damping resistor current values during scan and flyback have to be externally compensated in order to achieve a short settling time.
TDA8358J
For that purpose a compensation resistor RCMP is connected between pins OUTA and COMP. The value of RCMP is calculated by: ( V FB - V loss ( FB ) - V P ) x R D1 x ( R S + 300 ) R CMP = ------------------------------------------------------------------------------------------------------------( V FB - V loss ( FB ) - I coil ( peak ) x R coil ) x R M where: * Rcoil is the coil resistance * Vloss(FB) is the voltage loss between pins VFB and OUTA at flyback. East-west amplifier The east-west amplifier is current driven. The output can only sink currents of the diode modulator circuit. A feedback resistor (see Fig.4) has to be connected between the input and output of the inverting east-west amplifier in order to convert the east-west correction input current into an output voltage. The output voltage of the east-west circuit at pin OUTEW is given by: VOUTEW IINEW x REWF + VINEW The maximum output voltage is Vo(max) = 68 V, while the maximum output current of the circuit is Io(max) = 750 mA.
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Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VP VFB PARAMETER supply voltage flyback supply voltage CONDITIONS MIN. - - -
TDA8358J
MAX. 18 68 0.3
UNIT V V V
VVGND-EWGND voltage difference between pins VGND and EWGND Vn DC voltage pins OUTA and OUTEW pin OUTB pins INA, INB, INEW, GUARD, FEEDB, and COMP In DC current pins OUTA and OUTB pins OUTA and OUTB pins INA, INB, INEW, GUARD, FEEDB, and COMP pin OUTEW Ilu latch-up current input current into any pin; pin voltage is 1.5 x VP; Tj = 150 C during scan (p-p) at flyback (peak); t 1.5 ms note 1
- - -0.5
68 VP VP
V V V
- - -20 - -
3.2 1.8 +20 750 +200 - +350 4 15 +150 +85 +150
A A mA mA mA mA V W W C C C
input current out of any pin; -200 pin voltage is -1.5 x VP; Tj = 150 C Ves PEW Ptot Tstg Tamb Tj Notes 1. When the voltage at pin OUTA supersedes 70 V the circuit will limit the voltage. 2. Equivalent to 200 pF capacitance discharge through a 0 resistor. 3. Equivalent to 100 pF capacitance discharge through a 1.5 k resistor. electrostatic handling voltage east-west power dissipation total power dissipation storage temperature ambient temperature junction temperature note 5 machine model; note 2 human body model; note 3 note 4 -350 - - -55 -25 -
-4000 +4000 V
4. For repetitive time durations of t < 0.1 ms or a non-repetitive time duration of t < 5 ms the maximum (peak) east-west power dissipation PEW(peak) = 15 W. 5. Internally limited by thermal protection at Tj 170 C. THERMAL CHARACTERISTICS In accordance with IEC 747-1. SYMBOL Rth(j-c) Rth(j-a) PARAMETER thermal resistance from junction to case thermal resistance from junction to ambient in free air CONDITIONS VALUE 4 40 UNIT K/W K/W
2002 Sep 25
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Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier
TDA8358J
CHARACTERISTICS VP = 12 V; VFB = 45 V; fvert = 50 Hz; VI(bias) = 880 mV; Tamb = 25 C; measured in test circuit of Fig.3; unless otherwise specified. SYMBOL Supplies VP VFB Iq(P)(av) Iq(P) Iq(FB)(av) operating supply voltage flyback supply voltage average quiescent supply current quiescent supply current average quiescent flyback supply current note 1 during scan no signal; no load during scan 7.5 - - - 12 10 45 - 18 66 15 75 10 V V mA mA mA 2 x VP 45 PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Inputs A and B Vi(p-p) VI(bias) II(bias) Vloss(1) input voltage (peak-to-peak value) input bias voltage input bias current note 2 note 2 - 100 - note 3 Io = 1.1 A Io = 1.6 A Vloss(2) voltage loss second scan part note 4 Io = -1.1 A Io = -1.6 A Io(p-p) LE output current (peak-to-peak value) linearity error Io(p-p) = 3.2 A; notes 5 and 6 adjacent blocks non-adjacent blocks Voffset offset voltage across RM; Vi(dif) = 0 V VI(bias) = 200 mV VI(bias) = 1 V Voffset(T) VO Gv(ol) f-3dB(h) Gv Gv(T) PSRR offset voltage variation with temperature DC output voltage open-loop voltage gain high -3 dB cut-off frequency voltage gain voltage gain variation with temperature power supply rejection ratio note 10 across RM; Vi(dif) = 0 V Vi(dif) = 0 V notes 7 and 8 open-loop note 9 - - - - - - - - 80 - - - 0.5 x VP 60 1 1 - 90 15 20 40 - - - - 10-4 - K-1 dB mV mV V/K V dB kHz - - 1 1 2 3 % % - - - - - - 3.3 4.8 3.2 V V A - - - - 4.5 6.6 V V 1000 880 25 1500 1600 35 mV mV A
Outputs A and B voltage loss first scan part
2002 Sep 25
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Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier
SYMBOL Flyback switch Io(peak) Vloss(FB) maximum (peak) output current voltage loss at flyback t 1.5 ms note 11 Io = 1.1 A Io = 1.6 A Guard circuit VO(grd) guard output voltage IO(grd) = 100 A maximum leakage current IL(max) = 10 A VO(grd) = 0 V; not active VO(grd) = 4.5 V; active East-west amplifier Vo Vloss VI(bias) II(bias) output voltage voltage loss input bias voltage input bias current into pin INEW; note 13 Io = 100 mA Io = 500 mA Gv(ol) THD f-3dB(h) open-loop voltage gain harmonic distortion high -3 dB cut-off frequency - - - - - 2.5 11.5 30 0.5 - at pin OUTEW Io = 750 mA; note 12 - - 2 - - 2.5 5 - - 1 6 - - - - - 7.5 8 - - PARAMETER CONDITIONS MIN. TYP.
TDA8358J
MAX. 1.8 8.5 9
UNIT
A V V
7 18 10 2.5
V V A mA
VO(grd)(max) allowable guard voltage IO(grd) output current
68 5 3.2 - - - 1 1
V V V A A dB % MHz
2002 Sep 25
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Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier
Notes
TDA8358J
1. To limit VOUTA to 68 V, VFB must be 66 V due to the voltage drop of the internal flyback diode between pins OUTA and VFB at the first part of the flyback. 2. Allowable input range for both inputs: VI(bias) + Vi < 1600 mV and VI(bias) - Vi > 100 mV. 3. This value specifies the sum of the voltage losses of the internal current paths between pins VP and OUTA, and between pins OUTB and GND. Specified for Tj = 125 C. The temperature coefficient for Vloss(1) is a positive value. 4. This value specifies the sum of the voltage losses of the internal current paths between pins VP and OUTB, and between pins OUTA and GND. Specified for Tj = 125 C. The temperature coefficient for Vloss(2) is a positive value. 5. The linearity error is measured for a linear input signal without S-correction and is based on the `on screen' measurement principle. This method is defined as follows. The output signal is divided in 22 successive equal time parts. The 1st and 22nd parts are ignored, and the remaining 20 parts form 10 successive blocks k. A block consists of two successive parts. The voltage amplitudes are measured across RM, starting at k = 1 and ending at k = 10, where Vk and Vk+1 are the measured voltages of two successive blocks. Vmin, Vmax and Vavg are the minimum, maximum and average voltages respectively. The linearity errors are defined as: Vk - Vk + 1 a) LE = ------------------------- x 100% (adjacent blocks) V avg V max - V min b) LE = ------------------------------ x 100% (non adjacent blocks) V avg 6. The linearity errors are specified for a minimum input voltage at pin 1 or pin 2 of 300 mV. Lower input voltages lead to voltage dependent S-distortion in the input stage. 7. V OUTA - V OUTB G v ( ol ) = ------------------------------------------V FEEDB - V OUTB
8. Pin FEEDB not connected. 9. V FEEDB - V OUTB G V = ------------------------------------------V INA - V INB
10. VP(ripple) = 500 mV (RMS value); 50 Hz < fP(ripple) < 1 kHz; measured across RM. 11. This value specifies the internal voltage loss of the current path between pins VFB and OUTA. 12. This value specifies the internal voltage loss of the current path between pins OUTEW and EWGND. 13. Measured for REWF = 10 k; REWL = 30 ; Vo = 6 V. a) For Io = 100 mA and a voltage of 9 V at REWL connected to the line output transformer, the east-west amplifier input current (see Fig.4) is Ii = 300 A. b) For Io = 500 mA and a voltage of 21 V at REWL connected to the line output transformer, the east-west amplifier input current (see Fig.4) is Ii = 350 A.
2002 Sep 25
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Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier
APPLICATION INFORMATION
TDA8358J
handbook, full pagewidth
RGRD 4.7 k COMP 13 COMP. CIRCUIT Vi(p-p) GUARD VP 11 GUARD CIRCUIT M5 D2 D3 M2 3 VFB 9 C1 100 nF C2 100 nF
VP VFB
VI(bias) 0 I I(bias) INA 1 RCV1 2.2 k (1%) I i(dif) I I(bias) INB 2 RCV2 2.2 k (1%) Vi(p-p) VI(bias) 0 Ii(p-p) II(av) 0 Ii REWF 10 k VGND Ii M4 INPUT AND FEEDBACK CIRCUIT M1 D1
10 OUTA RL 3.2
12 FEEDB
RS 2.7 k CM 10 nF
RM 0.5
4 M3
OUTB
TDA8358J
INEW 5
M6
8 OUTEW REWL 30
6
7 EWGND
MGL873
Fig.3 Test diagram.
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10
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dbook, full pagewidth
2002 Sep 25
RGRD 12 k COMP 13 Vi(p-p) VI(bias) 0 COMP. CIRCUIT GUARD CIRCUIT INA 1 C5 2.2 nF TV SIGNAL PROCESSOR RCV1 2.2 k D1 INB 2 C6 2.2 nF RCV2 2.2 k INPUT AND FEEDBACK CIRCUIT
Philips Semiconductors
Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier
VP = 14 V GUARD VP 11 3 VFB 9 C3 100 nF C1 47 F (100 V) C4 100 nF VFB = 30 V C2 220 F
M5 D2 D3 M2 RCMP 500 k 10 OUTA M4 12 FEEDB RS 2.7 k RD1 270 deflection coil 5 mH 6 W66ESF RM 0.87 4 M3 OUTB
CD 47 nF RD2 1.5
11
Vi(p-p) VI(bias) 0 INEW 5 Ii(p-p) II(av) 0 Ii
M1
TDA8358J
M6
8 OUTEW REWL 12
to line output transformer
6 REWF 82 k VGND
7 EWGND
Product specification
MGL874
TDA8358J
fvert = 50 Hz; tFB = 640 s; II(bias) = 400 A; Ii(p-p) = 475 A; Io(p-p) = 2.4 A.
Fig.4 Application diagram.
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier
RM calculation Before calculating the measuring resistor (RM), the differential input voltage [Vi(dif)] has to be known. This voltage can be measured between pins INA and INB. The V i(dif)(p-p) calculation is as follows: R M = --------------------I o(p-p) Most of the TV signal processors from Philips have a current output. This current has to be converted by resistors at the input of the TDA8358J (RCV1 and RCV2). The voltage across these resistors can be calculated. The differential input voltage is given in the following equation (see also Fig 5): Vi(dif)(p-p) = Ii1(p-p) x RCV1 - [-Ii2(p-p)] x RCV2 Supply voltage calculation
TDA8358J
For calculating the minimum required supply voltage, several specific application parameter values have to be known. These parameters are the required maximum (peak) deflection coil current Icoil(peak), the coil impedance Rcoil and Lcoil and the measuring resistance of RM. The required maximum (peak) deflection coil current should also include the overscan. The deflection coil resistance has to be multiplied by 1.2 in order to take account of hot conditions. Chapter "Characteristics" supplies values for the voltage losses of the vertical output stage. For the first part of the scan the voltage loss is given by Vloss(1). For the second part of the scan the voltage loss is given by Vloss(2). The voltage drop across the deflection coil during scan is determined by the coil impedance. For the first part of the scan the inductive contribution and the ohmic contribution to the total coil voltage drop are of opposite sign, while for the second part of the scan the inductive part and the ohmic part have the same sign.
Ii1(p-p) II(bias) 0
1 C5 2.2 nF TV SIGNAL PROCESSOR RCV1 2.2 k
For the vertical frequency the maximum frequency occurring must be applied to the calculations. The required power supply voltage VP for the first part of the scan is given by: V P ( 1 ) = I coil ( peak ) x ( R coil + R M ) - L coil x 2I coil ( peak ) x f vert ( max ) + V loss ( 1 )
2 C6 2.2 nF RCV2 2.2 k
The required power supply voltage VP for the second part of the scan is given by: V P ( 2 ) = I coil ( peak ) x ( R coil + R M ) + L coil x 2I coil ( peak ) x f vert ( max ) + V loss ( 2 ) The minimum required supply voltage VP shall be the highest of the two values VP(1) and VP(2). Spread in supply voltage and component values also has to be taken into account. Flyback supply voltage calculation
Ii2(p-p) II(bias) 0
MBL520
Fig.5 Differential input voltage.
Values for these currents are, for instance: Ii(bias) = 400 A; Ii1(p-p) = Ii2(p-p) = 475 A. Therefore the differential input voltage be as follows: Vi(dif)(p-p) = 475 A x 2.2 k - (-475 A x 2.2 k) = 2.09 V
If the flyback time is known, the required flyback supply voltage can be calculated by the simplified formula: R coil + R M V FB = I coil ( p -p ) x -------------------------- t FB x 1-e where: L coil x = -------------------------R coil + R M
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Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier
The flyback supply voltage calculated this way is approximately 5% to 10% higher than required. Calculation of the power dissipation of the vertical output stage The power dissipation of the vertical output stage is given by the formula: PV = Psup - PL The power to be supplied is given by the formula: I coil ( peak P sup = V P x -----------------------) + V P x 0.015 [A] + 0.3 [W] 2 In this formula 0.3 [W] represents the average value of the losses in the flyback supply. The average external load power dissipation in the deflection coil and the measuring resistor is given by the formula: ( I coil ( peak ) ) P L = ------------------------------- x ( R coil + R M ) 3 Example Table 1 Application values VALUE 1.2 2.4 5 6 0.6 50 640 Calculated values VALUE 14 7.8 0.02 0.000641 30 8.91 3.74 5.17 UNIT V s V W W W UNIT A A mH Hz s
2
TDA8358J
Power dissipation calculation for the east-west stage In general the shape of the east-west output wave form is a parabola. The output voltage will be higher at the beginning and end of the vertical scan compared to the voltage at the scan middle, while the output current will be higher at the scan middle. This results in an almost uniform power dissipation distribution during scan. Therefore the power dissipation can be calculated by multiplying the average values of the output voltage and the output current of pin OUTEW. When verifying the dissipation the switch-on and switch-off dissipation should also be taken into account. Power dissipation during start-up can be 3 to 5 times higher than during normal operation. Heatsink calculation The value of the heatsink can be calculated in a standard way with a method based on average temperatures. The required thermal resistance of the heatsink is determined by the maximum die temperature of 150 C. In general we recommend a design for an average die temperature not exceeding 130 C. It should be noted that the heatsink thermal resistance Rth(h-a) found by performing a standard calculation will be lower then normally found for a vertical deflection stand alone device, due to the contribution of the EW power dissipation to this value. EXAMPLE Measured or known values: PEW = 3 W; PV = 6 W; Tamb = 40 C; Tj = 130 C; Rth(j-c) = 4 K/W; Rth(c-h) = 1 K/W. The required heatsink thermal resistance is given by: T j - T amb R th ( h - a ) = ------------------------ - ( R th ( j - c ) + R th ( c - h ) ) P EW + P V When we use the values known we find: 130 - 40 R th ( h - a ) = --------------------- - ( 4 + 1 ) = 5 K/W 3+6 The heatsink temperature will be: Th = Tamb + Rth(h-a) x Ptot = 40 + 5 x 9 = 85 C
SYMBOL Icoil(peak) Icoil(p-p) Lcoil Rcoil RM fvert tFB Table 2
SYMBOL VP RM + Rcoil (hot) tvert x VFB Psup PL PV
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Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier
Equivalent thermal resistance network The TDA8358J has two independent power dissipating systems, the vertical output circuit and the east-west circuit. It is recommended to verify the individual maximum (peak) junction temperatures of both circuits. Therefore the maximum (peak) power dissipations of the circuits and also the heatsink temperature should be measured. The maximum (peak) junction temperatures can be calculated by using an equivalent thermal network (see Fig.6). The network only includes the contribution of the maximum (peak) power dissipation PTRv(peak), being the dissipation of the most critical transistor internally connected to pins OUTA and VGND. The model assumes equivalent maximum (peak) power dissipations during the different vertical scan stages for all the functionally paired transistors. The calculated maximum (peak) junction temperatures should not exceed Tj = 150 C. EXAMPLE Measured or known values:
TDA8358J
* The east-west power dissipation: PEW = 3 W * The vertical power dissipation: PV = 6 W * The maximum (peak) power dissipation of the most critical transistor: PTRv(peak) = 5 W * The case temperature: Tc = 85 C. The IC total power dissipation is: Ptot = PEW + PV = 6 + 3 = 9 W It should be noted that the allowed IC total power dissipation is Ptot = 15 W (maximum value). The maximum (peak) temperature TP1(peak) is given by: * TP1(peak) = Tc + (PEW + PTRv(peak)) x Rth(P1-c) = 85 + (3 + 5) x 2.2 = 102.6 C The maximum (peak) junction temperatures for the output circuits are given by: * Tj(EW)(peak) = TP1(peak) + Rth(EW-P1) x PEW = 102.6 + 10.5 x 3 = 134.1 C * Tj(TRv)(peak) = TP1(peak) + Rth(TRv-P1) x PTRv(peak) = 102.6 + 5.2 x 5 = 128.6 C
handbook, halfpage
TEW(M)
TTRv(M)
Rth(EW-P1) 10.5 K/W PEW TP1(M) Rth(P1-c) 2.2 K/W Ptot Tc
Rth(TRv-P1) 5.2 K/W PTRv(M)
MGL872
Fig.6 Equivalent thermal resistance network.
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Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier
INTERNAL PIN CONFIGURATION PIN 1 SYMBOL INA EQUIVALENT CIRCUIT
TDA8358J
1
300
MBL100
2
INB
2
300
MBL102
3 4 6 9 10
VP OUTB VGND VFB OUTA
3 9
10
4 6
MGL869
5 7 8
INEW EWGND OUTEW
300 5
7
8
MGL868
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Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier
PIN 11 SYMBOL GUARD
300 11
TDA8358J
EQUIVALENT CIRCUIT
MGL870
12
FEEDB
300
12
MGL871
13
COMP
300 13
MGL875
2002 Sep 25
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Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier
PACKAGE OUTLINE DBS13P: plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm)
TDA8358J
SOT141-6
non-concave x D Dh
Eh
view B: mounting base side
d
A2
B j E A
L3
L
Q c vM
1 Z e e1 bp wM
13 m e2
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT141-6 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION A 17.0 15.5 A2 4.6 4.4 bp 0.75 0.60 c 0.48 0.38 D (1) 24.0 23.6 d 20.0 19.6 Dh 10 E (1) 12.2 11.8 e 3.4 e1 1.7 e2 5.08 Eh 6 j 3.4 3.1 L 12.4 11.0 L3 2.4 1.6 m 4.3 Q 2.1 1.8 v 0.8 w 0.25 x 0.03 Z (1) 2.00 1.45
ISSUE DATE 97-12-16 99-12-17
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Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier
SOLDERING Introduction to soldering through-hole mount packages This text gives a brief insight to wave, dip and manual soldering. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. Soldering by dipping or by solder wave The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joints for more than 5 seconds.
TDA8358J
The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Manual soldering Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds.
Suitability of through-hole mount IC packages for dipping and wave soldering methods SOLDERING METHOD PACKAGE DIPPING DBS, DIP, HDIP, SDIP, SIL Note 1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. suitable suitable(1) WAVE
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Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier
DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS
TDA8358J
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Preliminary data
Qualification
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2002 Sep 25
19
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/02/pp20
Date of release: 2002
Sep 25
Document order number:
9397 750 09635

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